The Hong Kong Polytechnic University (PolyU) has announced a breakthrough in transistor technology that could redefine the future of integrated circuits and artificial intelligence (AI) hardware. A research team led by Prof. Jianhua HAO, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, has engineered a novel tunnelling field-effect transistor (TFET) using 2D nanomaterials. This innovation overcomes the physical "Boltzmann limit," a fundamental barrier that has constrained the energy efficiency of traditional transistors for decades.
Conventional transistors operate through thermionic emission, where electrical charges are thermally excited over an energy barrier. This process requires a minimum gate voltage of 60 millivolts (mV) to switch the transistor on and off at room temperature. This threshold, known as the Boltzmann limit, sets a lower bound on the subthreshold swing (SS)—the voltage needed to change the current by a factor of ten—at 60 mV per decade. As a result, further miniaturization and energy reduction in conventional semiconductors have become increasingly challenging, hindering progress in high-performance electronics.
Prof. Hao's team circumvented this limitation by adopting quantum tunnelling, a phenomenon where charge carriers pass through an energy barrier rather than going over it. By creating an ultra-thin heterostructure of alternating layers of 2D bismuth and indium selenide using pulsed laser deposition, they achieved precise control over the layer structure. In its 2D form, bismuth—normally a semi-metal—transforms into a semiconductor, enabling efficient quantum tunnelling of charge carriers into indium selenide.
The resulting TFET demonstrated subthreshold swing values well below the 60 mV per decade limit, operating at room temperature on silicon substrates. Remarkably, the device required a gate-voltage range of only 160 mV, compared to 800 mV for conventional transistors, representing a five-fold reduction in operating voltage. This significant improvement translates to lower power consumption and faster switching speeds, essential for next-generation AI chips and advanced semiconductor applications.
Additionally, the TFET achieved a high output current alongside an exceptionally high ON/OFF current ratio, a challenge that has previously hindered experimental TFETs. This combination allows the device to drive multiple downstream logic gates while minimizing circuit delay, making it a practical candidate for integration into complex integrated circuits.
The research, conducted in collaboration with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design, has been published in the prestigious journal Science. The findings provide a solid foundation for ultra-low-power, high-performance computing, and could accelerate the development of energy-efficient AI hardware.
Prof. Hao emphasized the significance of the breakthrough: "By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications."
This innovation addresses a critical bottleneck in semiconductor technology, offering a path forward as conventional scaling approaches its physical limits. With the growing demand for AI capabilities, the need for more efficient transistors has never been greater. The PolyU-led team's work represents a significant step toward meeting that demand, potentially reshaping the landscape of microelectronics.
